A low-power CMOS multi-modulus dynamic frequency divider

Author

Sharaf, Khaled M.

Author_Institution

Integrated Circuits Lab., Ain-Sharas Univ., Cairo

fYear

2008

fDate

18-20 March 2008

Firstpage

1

Lastpage

9

Abstract

A low-power CMOS multi-modulus dynamic frequency divider designed in TSMC 0.13-mum CMOS process is presented. The divider core comprises a synchronous 3-stage ring oscillator gated by the input clock signal. Basic divide-by-two mode is analyzed in detail to determine the working frequency range in terms of intrinsic divider delay elements. Divide-by-three and four frequency bands have also been observed and studied but at a lower input swing supplied by a programmable differential clock buffer. The frequency divider features a triple-modulus (/2/3/4) in the 5.4-6 GHz frequency band and dissipates 140 muW from a supply voltage of 1V. The frequency divider output phase noise is better that of the input clock source by 6, 9 and 11 dB for /2, /3 and /4 mode, respectively.

Keywords

CMOS integrated circuits; clocks; frequency dividers; oscillators; CMOS multimodulus dynamic frequency divider; TSMC; divide-by-two mode; input clock signal; programmable differential clock buffer; size 0.13 mum; synchronous 3-stage ring oscillator; CMOS process; Clocks; Delay; Design engineering; Frequency conversion; Frequency synthesizers; Latches; Power dissipation; Radiofrequency integrated circuits; Ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 2008. NRSC 2008. National

Conference_Location

Tanta Univ.

Print_ISBN

978-977-5031-95-2

Type

conf

DOI

10.1109/NRSC.2008.4542381

Filename

4542381