Remote laboratory for testing processor cores in FPGA device

In the paper we present generic hardware verification structures for efficient testing of the custom processor cores in FPGA devices. Hardware verification environment consists of hardware debug structures: control machine, memory access port, input and output data buffers and interface logic. The verification structures are integrated and synthesized with the processor core under test and implemented on the FPGA device. The structures can be customized and easily integrated in the hardware development flow. A software support for the hardware verification consists of a data acquisition driver running on the server with HTML5 graphical interface. The software enables either local testing or setup of a remote laboratory for testing of the processor cores. The application of the remote laboratory in the educational process is presented. The presented hardware verification structures are optimized for testing the soft programmable processor cores and are vendor independent. The software support is based on open languages and protocols and the scripting tools enable quick customization. We present advantages of our solution compared to commercial general purpose on-chip logical analyzers. The benefit of our approach is that it can be used with the standard programmable design tools on the low cost platforms and provides two abstraction levels of debugging.