A 100MHz Digital Down Converter with modified FIR filter for wideband software-defined radios

Author

Liu, Hua-Ming ; Li, Guang-Jun ; Yan, Bo ; Li, Qiang

Author_Institution

Sch. of Commun. & Inf. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China

Volume

2

fYear

2010

fDate

1-3 Aug. 2010

Abstract

Digital Down Converter is one of the key technologies in Software Defined Radio. In Digital Down Converter how to realize a high-speed, high-order FIR filter is an interesting problem. This paper proposes a modified Distributed Arithmetic, in which speed is improved and memory is saved compared with the traditional Distributed Arithmetic. The presented FIR filter based on the modified Distributed Arithmetic has been implemented in the form of ASIC which was fabricated in a SMIC 0.13 μm CMOS process. The chip´s sample rate can reach 10MSPS in the 80MHz system clock.

Keywords

CMOS integrated circuits; FIR filters; convertors; software radio; ASIC; CMOS process; SMIC; digital down converter; frequency 100 MHz; modified FIR filter; system clock; wideband software-defined radios; Clocks; Converters; Finite impulse response filter; Low pass filters; Memory management; Random access memory; DDC; FIR filter; Modified Distributed Arithmetic;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics and Information Engineering (ICEIE), 2010 International Conference On

Conference_Location

Kyoto

Print_ISBN

978-1-4244-7679-4

Electronic_ISBN

978-1-4244-7681-7

Type

conf

DOI

10.1109/ICEIE.2010.5559748

Filename

5559748