DocumentCode :
1852931
Title :
Deriving a simulation input generator and a coverage metric from a formal specification
Author :
Shimizu, Kanna ; Dill, D.L.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
fYear :
2002
fDate :
2002
Firstpage :
801
Lastpage :
806
Abstract :
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a functional coverage metric are all created automatically from a single specification. Additionally, the process exploits the structure of a specification written with simple style rules. The methodology was used to verify a largescale I/O design from the Stanford FLASH project.
Keywords :
binary decision diagrams; circuit CAD; circuit simulation; formal specification; formal verification; logic CAD; RTL design verification; Stanford FLASH project; correctness checker; formal specification; functional coverage metric; functional interface specifications; large-scale I/O design; simulation environment; simulation input generator; Binary decision diagrams; Computational modeling; Computer bugs; Computer interfaces; Design engineering; Formal specifications; Laboratories; Permission; Protocols; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
ISSN :
0738-100X
Print_ISBN :
1-58113-461-4
Type :
conf
DOI :
10.1109/DAC.2002.1012732
Filename :
1012732
Link To Document :
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