14 b, 50 MS/s CMOS front-end sample and hold module dedicated to a pipelined ADC

Author

Chouia, Y. ; El-Sankary, K. ; Saleh, A. ; Sawan, M. ; Ghannouchi, F.

Author_Institution

Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada

Volume

1

fYear

2004

fDate

25-28 July 2004

Abstract

A high performance sample-and-hold (S/H) circuit intended a fast pipelined analog to digital converter was designed and implemented using a 0.18 μm CMOS process, the sampling rate of the proposed S/H module is 50 MS/s with a bandwidth of 20 MHz and a power supply of 1.8 V. Using switched capacitor differential topology, double bootstrapped switches and several native transistors, we optimized with VerilogA models the amplifier and the switches to end up with the optimized high performance circuit. The post layout simulation allowed to reach an SFDR of 88.6 dB for 20 MHz input signal. The circuit was integrated to other building blocks to construct a pipelined ADC which is now under fabrication.

Keywords

CMOS integrated circuits; HF amplifiers; analogue-digital conversion; bootstrap circuits; circuit optimisation; circuit simulation; integrated circuit layout; network topology; pipeline processing; sample and hold circuits; switched capacitor networks; 0.18 micron; 1.8 V; 14 bit; 20 MHz; CMOS front end sample and hold module; VerilogA models; amplifiers; circuit layout; circuit optimisation; circuit simulation; double bootstrapped switches; high performance sample and hold circuit; pipelined ADC; pipelined analog-digital converter; switched capacitor differential topology; transistors; Analog-digital conversion; Bandwidth; CMOS process; Circuit topology; Design optimization; Power supplies; Sampling methods; Switched capacitor circuits; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1354000

Filename

1354000