Reliable and energy-efficient digital signal processing

Author

Shanbhag, Naresh

Author_Institution

Dept. of ECE & Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

2002

fDate

2002

Firstpage

830

Lastpage

835

Abstract

This paper provides an overview of algorithmic noise-tolerance (ANT) for designing reliable and energy-efficient digital signal processing systems. Techniques such as prediction-based, error cancellation-based, and reduced precision redundancy based ANT are discussed. Average energy-savings range from 67% to 71% over conventional systems. Fluid IP core generators are proposed as a means of encapsulating the benefits of an ANT-based low-power design methodology. CAD issues resident in such a methodology are also discussed.

Keywords

CMOS digital integrated circuits; VLSI; circuit CAD; digital signal processing chips; error correction; integrated circuit design; integrated circuit noise; integrated circuit reliability; low-power electronics; redundancy; CAD issues; CMOS technologies; IC design; algorithmic noise-tolerance; broadband communications; deep submicron implementation; energy-efficient DSP systems; error cancellation-based technique; error control block; fluid IP core generators; low-power design methodology; low-power systems; prediction-based technique; reduced precision redundancy based technique; reliable DSP; Algorithm design and analysis; Broadband communication; CMOS technology; Digital signal processing; Energy efficiency; Integrated circuit noise; Semiconductor device noise; Signal processing algorithms; Very large scale integration; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings. 39th

ISSN

0738-100X

Print_ISBN

1-58113-461-4

Type

conf

DOI

10.1109/DAC.2002.1012737

Filename

1012737