A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS

A synthesizable all digital phase-locked loop (ADPLL) with an improved DCO and a frequency-bouncing-reduced algorithm is presented. The ADPLL covers 1.6-880 MHz frequency range while maintaining high frequency resolution. The synthesizable ADPLL can be easily migrated to different processes and foundries; requires less design time and maintain effort; and directly benefit from CMOS technology scaling. The PLL is fabricated in a 0.13-mum 1P6M high-Vt CMOS process and occupies an active area of 220 x 220 um². The PLL consumes a maximum power of 16 mW and has 114 ps peak-to-peak jitter at 880 MHz.