An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics

Author

Gu, Ruei Ting ; Huang, Wei Sheng ; Wang, Chien Chou ; Shiue, Wen Chi ; Ho, Tsung Yu ; Tsai, Chung Hua ; Tien, Tzu Ching ; Zhang-Jian, Da Jing ; Chiu, Sheng Yu ; Huang, Ing Jer ; Chang, Yun Nan ; Hsiao, Shen Fu ; Hong, Jin Hua ; Lee, Chung Nan ; Chiang, Mi

Author_Institution

Nat. Sun Yat-Sen Univ., Kaohsiung

fYear

2008

fDate

23-25 April 2008

Firstpage

59

Lastpage

62

Abstract

A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm². The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels with compression ratio up to 98%.

Keywords

computer graphics; consumer electronics; protocols; OpenGL ES 1.0; bus protocol error; consumer electronics; counting module; embedded circuitry; frequency 139 MHz; protocol checker; real-time bus tracer; tile-based 3D graphics; Consumer electronics; Costs; Engines; Geometry; Graphics; Hardware; Monitoring; Pipelines; Protocols; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4244-1616-5

Electronic_ISBN

978-1-4244-1617-2

Type

conf

DOI

10.1109/VDAT.2008.4542412

Filename

4542412