Debugging clock-data race failures caused by vulnerable design

Clock-data race on silicon may cause hold-time violations or other logic/timing failures. In this paper we illustrate that sometimes clock-data race exists on a chip because the design itself is vulnerable. If chip designers and DFT engineers do not handle the race carefully, the clock-data race may fail the test when the guardian margin for timing is not enough. With the increase of process variations at nanometer technologies, the clock-data race could become more unpredictable. We propose a software based silicon debug algorithm that identifies the triggered race clock(s) and the race paths associated with it.