DocumentCode
1853478
Title
A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization
Author
Chakraborty, Kanad ; Long, David E. ; Fishburn, John P. ; Singhal, Kishore ; Lun Ye ; Ortiz, Christopher
Author_Institution
Design Principles Res. Dept., Agere Syst., Murray Hill, NJ, USA
fYear
2002
fDate
2002
Firstpage
23
Lastpage
26
Abstract
Buffer insertion can be used very successfully for mitigation of crosstalk noise while simultaneously optimizing the effect of the insertion on the path delay. A vast majority of nets with crosstalk problems can be fixed by adding only a few buffers. This causes negligible place-and-route perturbations and allows for a convergent noise-loop closure methodology. This paper presents a novel algorithm for combining signal-integrity analysis with buffer insertion for noise and delay optimization after place-and-route.
Keywords
circuit layout CAD; circuit optimisation; crosstalk; delays; integrated circuit layout; integrated circuit noise; convergent noise-loop closure methodology; crosstalk noise; delay optimization; noise optimization; path delay; post-routing optimization; signal integrity-driven buffer insertion technique; signal-integrity analysis; Algorithm design and analysis; Bismuth; Capacitance; Circuit noise; Crosstalk; Delay; Design optimization; Integrated circuit interconnections; RLC circuits; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN
0-7803-7250-6
Type
conf
DOI
10.1109/CICC.2002.1012759
Filename
1012759
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