Title :
Generating several solutions for the scheduling problem in high-level synthesis
Author_Institution :
Lehrstuhl Rechnerstrukturen, Passau Univ., Germany
Abstract :
This paper presents a new approach for the scheduling problem in High-Level Synthesis. Starting with a maximal parallel data flow graph, the method adds successively edges to the graph so that all hardware constraints are observed. Every existing schedule can be managed in such a way. The result is a bundle of solutions with different scheduling variants. All solutions observe the same time- and hardware constraints as the original schedule. Succeeding binding algorithms can use these degrees of freedom and are able to generate better solutions
Keywords :
high level synthesis; logic design; scheduling; binding algorithms; hardware constraints; high-level synthesis; maximal parallel data flow graph; scheduling problem; Computational modeling; Digital systems; Hardware; High level synthesis; Optimal scheduling; Processor scheduling; Registers; Resource management; Scheduling algorithm; Time factors;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.528549
