Problems and prospects for electrical signaling [VLSI]

Summary form only given, as follows. The growing gap between on-chip gates and off-chip I/O bandwidth is reaching crisis proportions, yet signaling system designers continue to use inefficient and inappropriate circuit techniques for many chip-to-chip interconnections. For example, most chip-to-chip interconnect still uses CMOS inverters as transmitters and receivers, even though it would be difficult to imagine more unfavorable components for a signaling system. Processor-to-memory and processor-to-processor communication systems are still almost universally built using physical buses, transmission lines with multiple loads attached along their length. Though logically simple and convenient, these structures impose fundamental limits on signal speed that preclude their use above about 1-2 Gbaud, exact a heavy price in power dissipation, and are very difficult to engineer. Some have suggested replacing electrical signaling with optical interconnect; however, converting between optical and electrical signals is still expensive, and in any case, electrical signaling is far from its theoretical limits. With reasonable assumptions, the wiring embedded in a typical circuit board has bisection bandwidth of order 10 s of Tbit/s. Recent advances in high-speed serial link techniques point the way to unlocking a substantial fraction of this bandwidth. In CMOS, 1-2 Gbit/s links are fairly common, experimental 4 Gb/sec links have been demonstrated, and speeds up to 20 Gbits/s appear quite feasible