Title :
A 62–66.1GHz phase-locked loop in 0.13um CMOS technology
Author :
Tsai, Kun-Hung ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
This paper presents a 62-66.1 GHz phase-locked loop (PLL) in 0.13 um CMOS process. By employing a modified wide-range injection-locked frequency divider, the proposed PLL demonstrates the output frequency from 62 to 66.1 GHz which allowing wideband application in unlicensed 60 GHz radio. As the PLL operates at 66.09 GHz, the measured phase noise at 1 MHz offset is -74.5 dBc/Hz. The proposed circuit consumes a power of 89 mW from a 1.5 V supply voltage.
Keywords :
CMOS integrated circuits; frequency dividers; phase locked loops; CMOS technology; frequency 62 GHz to 66.1 GHz; injection-locked frequency divider; phase-locked loop; power 89 mW; size 0.13 mum; voltage 1.5 V; wideband application; CMOS process; CMOS technology; Circuits; Frequency conversion; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Power measurement; Wideband; CMOS; Phase-locked loop; clock generator; frequency dividers;
Conference_Titel :
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1616-5
Electronic_ISBN :
978-1-4244-1617-2
DOI :
10.1109/VDAT.2008.4542425
