DocumentCode
1853656
Title
The architecture of dual-mode FPGA embedded system blocks
Author
Lin, Ernie ; Wilton, Steven J E
Author_Institution
Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada
fYear
2002
fDate
2002
Firstpage
67
Lastpage
70
Abstract
Recently, it has been shown that unused on-chip memories can be valuable when they are used to implement logic. This paper explores how different memory architecture parameters affect its ability to implement logic in dual-mode FPGA embedded system blocks. It is shown that the optimum memory architecture has a depth of 32 or 64 words, and that each word should contain 16 bits.
Keywords
embedded systems; field programmable gate arrays; logic CAD; memory architecture; 16 bit; dual-mode FPGA; embedded system blocks; memory architecture parameters; optimum memory architecture; unused on-chip memories; Circuits; Computer architecture; Embedded system; Field programmable gate arrays; Logic arrays; Logic design; Logic devices; Memory architecture; Programmable logic arrays; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN
0-7803-7250-6
Type
conf
DOI
10.1109/CICC.2002.1012768
Filename
1012768
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