DocumentCode
1853683
Title
A hardware/software co-solution to achieving high throughput required by motion estimation part in H.264/AVC HDTV real-time application
Author
Chen, Zhenxing ; Ikenaga, Takeshi ; Goto, Satoshi
Author_Institution
Grad. Sch. of Inf., Waseda Univ., Kitakyushu
fYear
2008
fDate
23-25 April 2008
Firstpage
128
Lastpage
131
Abstract
The high throughput required by Motion Estimation (ME) part in H.264/AVC High Definition TV (HDTV) real-time application is very difficult to achieve. Currently one kind of the solutions to this problem is multipling the processing element (PE) array to construct redundant PE array structure. Although redundant structure can take advantages of parallel processing to achieve high throughput, meanwhile it bring in linear increasing of hardware cost. In this paper, a hardware/software co-solusion is proposed to achieve the required throughput of ME part in H.264/AVC HDTV realtime application. In software side, one adaptive search range (ASR) algorithm which is previously proposed by us [12] is firstly introduced and then experimentally proved can improve the throughput 11.48 times averagely in HDTV1080p video sequence. In hardware side, a previously proposed architecture called SAD-tree [17] is firstly introduced. Then based on this architecture, optimization that increase the frequence is proposed. The hardware implementing result of the optimized architecture shows the proposed optimization can triple the frequence. Finally, it is illustrated that the hardware/software co-solution can help to achieve the required throughput.
Keywords
high definition television; motion estimation; video coding; AVC; H.264; HDTV1080p video sequence; SAD tree; adaptive search range algorithm; hardware cosolution; motion estimation; parallel processing; software cosolution; Application software; Automatic voltage control; Computer architecture; Frequency; HDTV; Hardware; Motion estimation; Parallel processing; TV; Throughput; ASR; ME; SAD-tree; required throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-1616-5
Electronic_ISBN
978-1-4244-1617-2
Type
conf
DOI
10.1109/VDAT.2008.4542429
Filename
4542429
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