Title :
An Enhancer of Memory and Network for Cluster and its Applications
Author :
Tanabe, Noboru ; Nakajo, Hironori
Author_Institution :
Toshiba
Abstract :
Introduction of multi-core structures has not led to a decline in the rapid performance improvement of COTS CPU recently. On the other hand, the performance of memory and I/O systems is insufficient to catch up with that of COTS CPU. In this paper, with a view to realizing high-performance computer systems not only for HPC but also for Google-like servers, we propose concepts concerning memory systems and network systems with large extended memory. We introduce DIMMnet-3, which is a practical solution to enhance memory system and I/O system of PC, and Toshiba Cell Reference Set. Examples of the killer applications of this new type of hardware are presented. Communication mechanisms named LHS and LHC are also proposed. These are architectures for reducing latency for mixed messages with small controlling data and large acknowledge data. The latency evaluation of them is shown.
Keywords :
pattern clustering; COTS CPU; DIMMnet; Toshiba Cell Reference Set; latency evaluation; memory systems; memory-network enhancer; multicore structures; Agriculture; Bandwidth; Bridges; Computer architecture; Computer networks; Costs; Degradation; Delay; Distributed computing; Memory management; Memory system; Network interface; PC cluster;
Conference_Titel :
Parallel and Distributed Computing, Applications and Technologies, 2008. PDCAT 2008. Ninth International Conference on
Conference_Location :
Otago
Print_ISBN :
978-0-7695-3443-5
DOI :
10.1109/PDCAT.2008.59
