A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

Author

Tachibana, F. ; Hirabayashi, O. ; Takeyama, Y. ; Shizuno, M. ; Kawasumi, A. ; Kushida, K. ; Suzuki, A. ; Niki, Y. ; Sasaki, Seishi ; Yabe, Tatsuro ; Unekawa, Y.

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

49

Issue

1

fYear

2014

fDate

Jan. 2014

Firstpage

118

Lastpage

126

Abstract

This paper presents circuit techniques to reduce both active and standby mode power, especially at room temperature (RT). A bit-line power calculator is used to adaptively set the cell supply voltage (VCS) in the active mode. A digitally controllable retention circuit regulates VCS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28-nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25 ^°C is reduced by 27% and 85%, respectively.

Keywords

CMOS integrated circuits; SRAM chips; power consumption; power supply circuits; BL power calculator; CMOS technology; RT; VCS; active mode power reduction; bit-line power calculator; cell supply voltage; circuit techniques; digitally controllable retention circuit; dual-power-supply SRAM; power consumption; room temperature; size 28 nm; standby mode power reduction; temperature 25 C; temperature 293 K to 298 K; Calculators; Logic gates; Power demand; SRAM cells; System-on-chip; Bit-line power; SRAM; digital control; low power; replica BL; retention circuit;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2013.2280312

Filename

6605611