A burn-in tolerant dynamic circuit technique

Time, cost and efficiency of burn-in test are severely impacted by the required functionality of leaky sub-130 nm dynamic circuits during the burn-in. In this paper, we present an efficient keeper technique, which is active during the burn-in, and inactive at normal operating condition. As a consequence, dynamic circuits remain functional at burn-in without relaxing the maximum burn-in condition, and without any significant performance degradation at normal operating conditions. Compared to the conventional technique, and at the same level of burn-in robustness, up to 17% higher performance has been observed at normal operating condition across 2-to-6 way dynamic gates in a projected 100 nm technology.