A study on electrical design, modeling and validation methods for 1st & 2nd level high-speed interconnects

This paper investigates various options for 1st & 2nd level high-density interconnect technologies enabling next generation 10-20 Gbps/channel chip-to-chip link speed. In comparison to current technologies, the new technology options include thinner dielectric substrate, thinner copper for signal layer, lower loss dielectric material, Cu-alloy spring LGA (land-grid array) sockets, and conductive elastomer LGA sockets. In the evaluation of each technology, the modeling and validation methods are to be electrically accurate, mechanically stable and practically realizable. With these concepts in mind, various test coupons, measurements and modeling setups, and fixtures were designed to investigate various aspects of high-speed IO signal integrity impacted by different stack-ups, dielectric substrate materials and socket pin technologies. This paper highlighted some representative cases of modeling and validation methods specifically developed for Intel CPU chip-carrier packages and sockets.