DocumentCode
1853779
Title
High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies
Author
Chung-Hui Chen ; Fang, Yean-Kuen ; Tsai, Chien-Chun ; Tu, Shen ; Mark, K.L. ; Chen, Mark K L ; Chang, Mi-Chang
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2002
fDate
2002
Firstpage
89
Lastpage
92
Abstract
A new high voltage tolerant (HVT) ESD design adopts one forward biased P+/N-well diode in series of one stacked NMOS to reduce the total capacitance and maintain the high ESD performance is proposed and implemented by 0.18 μm CMOS technologies. The measured HBM and MM ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.
Keywords
CMOS analogue integrated circuits; VLSI; capacitance; electrostatic discharge; integrated circuit design; integrated circuit modelling; 0.18 micron; 250 fF; 550 V; 6 kV; ESD; HBM; MM; analog applications; deep submicron CMOS; forward biased P+/N-well diode; high voltage tolerant design; input capacitance; total capacitance; Atherosclerosis; Bonding; CMOS technology; Capacitance measurement; Clamps; Electrostatic discharge; MOS devices; Protection; Semiconductor diodes; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN
0-7803-7250-6
Type
conf
DOI
10.1109/CICC.2002.1012773
Filename
1012773
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