Title :
A 300MHz, 48mW analog front-end design for IEEE 802.3an 10GBase-T Ethernet
Author :
Chuang, Kai Hsiang ; Yeh, Jyh Yih ; Wang, Chao Shiun ; Wang, Chorng Kuang
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
This paper presents a receiver analog front-end (AFE) for 10GBase-T Ethernet system. The AFE can provide 14 dB voltage gain with 9 dB gain control range, and the gain step is 1.5 dB with +/-0.25 dB gain error. The analog front-end -3 dB bandwidth is 300 MHz. The 3rd harmonic distortion (HD3) is lower than -50 dB. It consumes 48 mW for 1.8 V supply voltage. This AFE is fabricated in 0.18-mum 1P6M CMOS technology and the chip area is 0.88times0.82 mm2.
Keywords :
CMOS analogue integrated circuits; harmonic distortion; local area networks; CMOS technology; IEEE 802.3an Ethernet; frequency 300 MHz; harmonic distortion; power 48 mW; receiver analog front-end; voltage gain; Bandwidth; CMOS technology; Circuit synthesis; Electronics packaging; Ethernet networks; Filters; Function approximation; Gain control; Switches; Transconductance; CMOS analog integrated circuits; Ethernet; Gm-C filter; automatic tuning loop; continuous time filter; current reused Gm cell;
Conference_Titel :
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1616-5
Electronic_ISBN :
978-1-4244-1617-2
DOI :
10.1109/VDAT.2008.4542435
