DocumentCode
1853824
Title
Realization of sequential circuits by look-up table rings
Author
Sasao, Tsutoniu ; Nakahara, Hiroki ; Matsuura, Munehiro ; Iguchi, Yukihiro
Author_Institution
Kyushu Inst. of Technol., Iizuka, Japan
Volume
1
fYear
2004
fDate
25-28 July 2004
Abstract
The LUT ring is a new type of memory-based realization of a sequential circuit that requires much smaller memory than conventional methods. In this paper, a method to realize a sequential circuit by a look-up table (LUT) ring is presented. The sequential circuit consists of a combinational part and feedback flip-flops. The combinational part is represented by a set of LUT cascades, and they are sequentially emulated by the LUT ring. The LUT ring uses two types of clocks: one evaluates the combinational part, and the other is the clock for state transitions of the sequential circuit. We present a method to reduce the clock period for state transitions, given limited memory size.
Keywords
circuit feedback; flip-flops; programmable logic arrays; random-access storage; reconfigurable architectures; sequential circuits; table lookup; combinational part; feedback flip flops; lookup table rings; memory based realization; programmable logic arrays; reconfigurable architectures; sequential circuits; state transition; Binary decision diagrams; Clocks; Flip-flops; Hardware; Programmable logic arrays; Rails; Random access memory; Reconfigurable architectures; Sequential circuits; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN
0-7803-8346-X
Type
conf
DOI
10.1109/MWSCAS.2004.1354041
Filename
1354041
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