A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs

Author

Fazan, P.C. ; Okhonin, Serguei ; Nagoga, Mikhail ; Sallese, Jean-Michel

Author_Institution

Innovative Silicon Solutions, Le Landeron, Switzerland

fYear

2002

fDate

2002

Firstpage

99

Lastpage

102

Abstract

A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.

Keywords

CMOS digital integrated circuits; DRAM chips; cellular arrays; integrated circuit reliability; memory architecture; silicon-on-insulator; 1-transistor capacitor-less memory cell; cell area; compact memory architecture; data retention; device operation principles; eDRAM; embedded DRAMs; floating body effect; partially depleted silicon on insulator; pure logic SOI technology; reliability; CMOS technology; Costs; Intrusion detection; Logic arrays; Logic devices; MOS devices; MOSFET circuits; Random access memory; Silicon on insulator technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012775

Filename

1012775