Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits

This paper studies two-input gate behaviors which are tolerant to any kind of gate delay variations. It is claimed that any circuit´s behavior can be transformed, refined to a composition of such steady gate´s behaviors. Such a refinement provides circuits built of two-input NAND, NOR gates and inverters which are free of hazards under arbitrary finite gate delays if each input signal transition is acknowledged by some output one in the behaviors to be realized. Experimental results show essential advantage of suggested approach over the methods used by modern tool for synthesis of speed-independent circuits.