New voltage level shifting circuits for low power CMOS interface applications

A new design method for level shifting circuits is presented in this paper. We propose two level shifting circuits that reduce problems that exist in complementary level shifting circuits described previously. Using HSPICE parameters of a 0.35 μm CMOS process, simulations have been performed under various capacitive loading and operating conditions. The simulations show that our design method can achieve 16.6% low-to-high propagation delay decrease and 27.2% low-to-high power delay product improvement when converting 3.3 V to 5 V compared with conventional level shifting circuits. In addition, as the working voltages being converted are reduced, the design yields still greater advantage without degrading circuit performance.