Optimized Component Labeling Algorithm for Using in Medium Sized FPGAs

Connected component labeling is a task that assigns unique IDs to the connected components of a binary image. The main contribution of this paper is to present a hardware connected component labeling algorithm for k-concave binary images designed and implemented in FPGA. Pixels of a binary image are given to the FPGA in raster order, and the resulting labels are also output in the same order. The advantage of our labeling algorithm is low latency and to use FPGA effectively. We have implemented our hardware labeling algorithm in an Altera Stratix Family FPGA, and evaluated the performance. The implementation result shows that for a 20-concave binary image of 2048 times 2048, our connected component labeling algorithm runs in approximately 72 ms and its latency is approximately 2.9 ms.