Automatic generation of VHDL code for neural applications

We report on a structured design methodology for neural hardware based on a VHDL code which can be implemented on a FPGA or used to create an ASIC. This code, dubbed virtual neuro-processor (VNP), is generated automatically from within the neural networks design and simulation environment and supports several network architectures. Error backpropagation learning can be supported by the VNP, thus allowing for the implementation of feedforward networks with on-chip training capability. The main advantage gained from the VNP-concept is that it highly automates and structures the design of (application specific) neural hardware. It thus considerably shortens the development time of such devices and ensures a high-quality design process