DocumentCode :
1853974
Title :
A synchronous high-speed, high-accuracy, loser-take-all circuit
Author :
Wilamowski, Bogdan M. ; Jordan, Don L.
Author_Institution :
Dept. of Electr. Eng., Wyoming Univ., Laramie, WY, USA
Volume :
4
fYear :
1999
fDate :
1999
Firstpage :
2306
Abstract :
Presents an accurate current mode synchronous loser-take-all circuit based on a simple regenerative pair. The regenerative pair and the related resetting transistors lead to a circuit requiring only four transistors, seven for deep binary tree structures. It achieves its high speed through regenerative feedback. The basic circuit requires no current mirrors and has only parasitic losses, resulting in high accuracy. The paper also includes simulation results for a single LTA circuit with two inputs and for a sixty-four input, six-layer, binary tree circuit
Keywords :
MOS integrated circuits; current-mode circuits; feedback; neural chips; transistors; deep binary tree structures; parasitic losses; regenerative feedback; regenerative pair; resetting transistors; sixty-four input six-layer binary tree circuit; synchronous high-speed high-accuracy loser-take-all circuit; Binary trees; Circuit simulation; Fuzzy logic; Fuzzy neural networks; Latches; Mirrors; Parasitic capacitance; RLC circuits; Signal processing; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks, 1999. IJCNN '99. International Joint Conference on
Conference_Location :
Washington, DC
ISSN :
1098-7576
Print_ISBN :
0-7803-5529-6
Type :
conf
DOI :
10.1109/IJCNN.1999.833423
Filename :
833423
Link To Document :
بازگشت