Title :
High-performance and low-power challenges for sub-70 nm microprocessor circuits
Author :
Krishnarnurthy, R.K. ; Alvandpour, Atila ; De, Vivek ; Borkar, Shekhar
Author_Institution :
Microprocessor Res., Intel Corp., Hillsboro, OR, USA
Abstract :
CMOS technology scaling is becoming difficult beyond 70 nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are described.
Keywords :
CMOS digital integrated circuits; VLSI; delays; leakage currents; low-power electronics; microprocessor chips; nanoelectronics; 70 nm; CMOS technology scaling; circuit techniques; global on-chip interconnect scaling; high-performance microprocessors; large-signal cache arrays; large-signal register files; leakage power dissipation; leakage power reduction techniques; leakage-tolerant techniques; low-power microprocessors; sub 70 nm node; switching power dissipation; switching power reduction techniques; CMOS technology; Central Processing Unit; Circuit noise; Clocks; Dynamic voltage scaling; Frequency; Integrated circuit interconnections; Microprocessors; Power generation; Registers;
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
DOI :
10.1109/CICC.2002.1012781
