DocumentCode
1853999
Title
A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)
Author
Tokumasu, Motokl ; Fujii, Hiroshige ; Ohta, Masako ; Fuse, Tsunealu ; Kameyama, Atsushi
Author_Institution
Corporate Res. & Dev. Center, Toshiba Corp., Kanagawa, Japan
fYear
2002
fDate
2002
Firstpage
129
Lastpage
132
Abstract
A new reduced clock-swing flip-flop, named NAND-type Keeper Flip-Flop (NDKFF) is proposed. Compared with other conventional reduced clock-swing flip-flops such as HSFF and RCSFF, NDKFF features a simple configuration, which does not have additional clock drivers or does not have additional nand/or p-wells. Compared with the hybrid-latch flip-flop, 52% of the flip-flop power and 64% of the clocking power are saved in the case of 0.25 μm CMOS technology. Moreover CLK-to-Q delay is comparable to that of conventional C2MOS-type master-slave flip-flop.
Keywords
CMOS logic circuits; NAND circuits; flip-flops; logic gates; low-power electronics; 0.25 micron; CLK-to-Q delay; CMOS technology; NAND-type keeper flip-flop; reduced clock-swing flip-flop; CMOS technology; Clocks; Degradation; Delay; Energy consumption; Flip-flops; Large scale integration; MOSFETs; Personal communication networks; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN
0-7803-7250-6
Type
conf
DOI
10.1109/CICC.2002.1012782
Filename
1012782
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