A low power adaptive filter using dynamic reduced 2´s-complement representation

We describe the IC implementation and testing of a low-power adaptive FIR filter. A new technique is used in its implementation, one that can be employed in other digital signal processing applications where input signals have large dynamic ranges. We propose the use of a reduced 2´s complement signal representation to conditionally disable the internal signal transitions in the most-significant-bits of a data path. The key idea is to generate the signal representation dynamically according to the signal magnitude. The proposed technique retains all of the easy-to-implement properties of the widely-used 2´s complement number representation and is particularly suitable for the implementation of arithmetic operations. Over a 32% power savings has been achieved in our adaptive filter application.