A Petri net approach to the design of processor array architectures

In this paper, a methodology for deriving processor array architectures that meet desired specifications for nested-loop algorithms is introduced. The methodology is based upon the construction of a Petri net model for the dependencies of the algorithm, the development of a forest of reachability trees for this model and the creation of an execution graph. Different executions of the algorithm are found on the reachability tree forest through a proposed function, leading to different architectures that implement the algorithm. The main advantage of this method is that it may easily lead to non-homogeneous architectures