Title :
A 4-PAM adaptive analog equalizer for backplane interconnections
Author :
Huang, Yen-Chuan ; Chen, Qui-Ting ; Lee, Tai-Cheng
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
Increasing of data rate has created a major challenge for electronic circuits used at the interface of the backplane physical layer links. As the data rate increases above Gb/s, intersymbol interference (ISI) becomes a critical issue in received signal quality, limiting the achievable transmission speed and distance over channels. A 4-PAM (pulse amplitude modulation) adaptive analog equalizer is proposed to compensate the FR-4 PCB backplane interconnections by using a sum- feedback filter (SFF), relaxing the design requirement of the conventional analog feed-forward equalizers (FFE). Fabricated in a 0.13- mum digital CMOS technology, the analog equalizer recovers 14 Gb/s random data transmitted over FR-4 PCB copper channels.
Keywords :
adaptive equalisers; pulse amplitude modulation; 4-PAM adaptive analog equalizer; FR-4 PCB backplane interconnection; analog feedforward equalizers; backplane physical layer links; electronic circuits; intersymbol interference; pulse amplitude modulation; received signal quality; sum-feedback filter; Amplitude modulation; Backplanes; CMOS technology; Electronic circuits; Equalizers; Feedback; Integrated circuit interconnections; Intersymbol interference; Physical layer; Pulse modulation;
Conference_Titel :
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1616-5
Electronic_ISBN :
978-1-4244-1617-2
DOI :
10.1109/VDAT.2008.4542447