Title :
A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 μm CMOS technology
Author :
Kuo, Henry ; Verbauwhede, Ingrid ; Schaumont, Patrick
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
In October 2000 the National Institute of Standard and Technology (NIST) chose the Rijndael algorithm as the new Advanced Encryption Standard (AES). In this paper we present an ASIC implementation of the Rijndael core. The core includes a non-pipelined encryption datapath with an on-the-fly key schedule data path. At a nominal 1.8 V, the IC runs at 125 MHz resulting in a throughput of 2.29 Gbit/s while consuming 56 mW. At 1.95 V, the chip can operate up to 154 MHz with an equivalent throughput of 2.8 Gbit/s and consumes 82 mW.
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; cryptography; digital signal processing chips; high-speed integrated circuits; low-power electronics; 0.18 micron; 1.8 to 1.95 V; 125 to 154 MHz; 2.29 to 2.8 Gbit/s; 56 to 82 mW; ASIC implementation; Advanced Encryption Standard; CMOS technology; Rijndael algorithm; Rijndael core; nonpipelined Rijndael AES encryption IC; nonpipelined encryption datapath; on-the-fly key schedule data path; Application specific integrated circuits; CMOS integrated circuits; CMOS technology; Clocks; Cryptography; Hardware; NIST; Output feedback; Throughput; Wireless LAN;
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
DOI :
10.1109/CICC.2002.1012785
