A low-power highly-integrated MPEG1/2 audio layer 3 (MP3) decoder for CD-based systems

Author

Cloetens, Henri ; Hahn, Reinhard ; Hooser, Bridget ; Lenke, Frank

Author_Institution

Broadband & Entertainment Solutions Div., Motorola, Munich, Germany

fYear

2002

fDate

2002

Firstpage

171

Lastpage

174

Abstract

The system design and the chip implementation aspects of an MPEG1/2 audio layer 3 (MP3) decoder chip suitable for Compact Disc (CD) based systems is discussed. A new innovative chip architecture is presented which addresses the low-power requirements of portable applications. This utilizes an optimum split between control processing tasks and signal processing code. The architecture was implemented using a synthesizable System-on-a-Chip approach. The chip has been fabricated in 0.18 μm CMOS technology. The silicon area is 16 mm² and operates at a minimum of 140 MHz, achieving up to 80 hours of playtime. This low-power approach outperforms other commercially available solutions.

Keywords

CMOS digital integrated circuits; audio coding; audio discs; decoding; low-power electronics; reduced instruction set computing; system-on-chip; 0.18 micron; 140 MHz; 32 bit; 32-bit RISC processor; 80 hour; CD-based systems; CMOS technology; compact disc based systems; control processing tasks; enhanced multiply-accumulate unit; innovative chip architecture; low-power highly-integrated MPEG1/2 audio layer 3 decoder; signal processing code; silicon area; synthesizable system-on-a-chip approach; variable-length introduction set; CMOS technology; Control systems; Decoding; Digital audio players; Hardware; IEC standards; ISO standards; Process control; Signal processing algorithms; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012791

Filename

1012791