An 80 MHz 8th-order bandpass ΔΣ-modulator with a 75 dB SNDR for IS-95

Author

Salo, T. ; Lindfors, S. ; Halonen, K.

Author_Institution

Electron. Circuit Design Lab., Helsinki Univ. of Technol., Finland

fYear

2002

fDate

2002

Firstpage

179

Lastpage

182

Abstract

A fully-differential 8th-order cascade bandpass ΔΣ-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 μm CMOS technology and consumes 37 mW from a 3.0 V supply.

Keywords

CMOS integrated circuits; cascade networks; delta-sigma modulation; frequency convertors; radio receivers; signal sampling; 0.35 micron; 1.25 MHz; 20 MHz; 3 V; 37 mW; 60 MHz; 80 MHz; CMOS technology; IF-receiver; IS-95; analog to digital conversion; digital intermediate frequency; direct signal sampling; frequency downconversion; fully-differential 8th-order cascade bandpass ΔΣ-modulator; intermediate frequency; peak SNDR; power consumption; sampling frequency; CMOS technology; Circuits; Digital signal processing; Filters; Frequency conversion; Noise shaping; Quantization; Sampling methods; Signal resolution; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012793

Filename

1012793