Title :
A 1-GS/s CMOS 6-bit flash ADC with an offset calibrating method
Author :
Chang, Chih Hsiang ; Hsiao, Chih Yi ; Yang, Ching Yuan
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung
Abstract :
In this paper a 1-GS/s 6-bit flash type analog-to-digital converter (ADC) is designed in 0.18-mum one-poly six-metal CMOS. An offset calibrating method is used to improve the performance of ADC. To reduce the input capacitance of the ADC and the amount of calibration circuit, the active interpolation technique is applied. Measured results show the ADC achieves a SNDR of 32.5 dB for a 7 MHz input at 1 GS/s, and 25.4 dB for a 108-MHz input. The power consumption is 550 mW at 1 GS/s from a 1.8-V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; interpolation; CMOS flash ADC; active interpolation; analog-to-digital converter; frequency 108 MHz; frequency 7 MHz; offset calibrating method; one-poly six-metal CMOS; voltage 1.8 V; Analog-digital conversion; Calibration; Capacitance; Counting circuits; Energy consumption; Interpolation; Latches; Multiplexing; Resistors; Voltage;
Conference_Titel :
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1616-5
Electronic_ISBN :
978-1-4244-1617-2
DOI :
10.1109/VDAT.2008.4542455
