Title :
A multi-bit sigma-delta ADC for multi-mode receivers
Author :
Miller, Matthew R. ; Petrie, Craig S.
Author_Institution :
Integrated Circuits Technol. Res. Lab., Motorola Inc., Schaumburg, IL, USA
Abstract :
A 2.7-volt ΣΔ modulator with a 6-bit quantizer is fabricated in a 0.18 μm CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.
Keywords :
CMOS integrated circuits; integrated circuit noise; low-power electronics; radio receivers; sigma-delta modulation; ΣΔ modulator; 0.18 micron; 1.92 MHz; 2.7 V; 23 MHz; 30 mW; 46 MHz; 50 mW; 6-bit quantizer; 625 kHz; CMOS process; SFDR; SNR; high linearity; multi-bit sigma-delta ADC; multi-mode receivers; noise-shaped dynamic element matching; power consumption; power dissipation; quantizer offset chopping; wide bandwidth; Bandwidth; CMOS process; Cellular phones; Circuits; Delta-sigma modulation; Linearity; Noise shaping; Receivers; Sampling methods; Switches;
Conference_Titel :
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN :
0-7803-7250-6
DOI :
10.1109/CICC.2002.1012795
