Title :
Path delay ATPG for standard scan design
Author :
Wittmann, Hannes ; Henftling, Manfred
Author_Institution :
Dept. of Electr. Eng., Tech. Univ. Munchen, Germany
Abstract :
Path delay fault test generation for standard scan design is topic of this work. A twenty-valued and a nine-valued logic are presented that are best-suited for the generation of robust and nonrobust tests. The scan design is used in two different ways: functional justification and scan shifting. Excellent experimental results considering all functional paths of benchmark circuits demonstrate the effectiveness of our approach
Keywords :
automatic test software; boundary scan testing; combinational circuits; integrated circuit testing; integrated logic circuits; logic CAD; logic design; logic testing; benchmark circuits; functional justification; nine-valued logic; path delay fault test generation; scan shifting; standard scan design; twenty-valued logic; Automatic test pattern generation; Circuit faults; Circuit testing; Delay; Electronic design automation and methodology; Flip-flops; Latches; Logic testing; Proposals; Test pattern generators;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.528552
