Algorithmic factorisation for low power FPGA implementations through increased data locality

Power consumption is a key design consideration particularly in FPGA-based DSP implementations where flexibility comes at the expense of power hungry interconnect. The paper presents a system level low power methodology promoting short regular interconnect through increased data locality. The recursive nature of DSP algorithms is leveraged to achieve locally interconnected processing clusters through factorisation and index mapping allowing the processing nodes to be mapped into hardware in a power efficient manner. The approach is applied to an FFT example giving large reductions in interconnect length. Power and capacitance results measured from a working implementation on a Virtex-II Pro platform are presented, demonstrating a performance power gain of 36-37% and area reduction of 61% when compared to a 64-point Xilinx FFT core.