DocumentCode
1854515
Title
Path sensitization of combinational circuits and its impact on clocking of sequential systems
Author
LLopis, R. Peset
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1995
fDate
18-22 Sep 1995
Firstpage
210
Lastpage
215
Abstract
The design of high performance ICs requires accurate critical path analysis tools, to verify and design optimal clocking schemes. A theoretical basis is presented, which allows comparison of several path analysis approaches. Finally, an optimal and correct clocking scheme is presented, which does not suffer from the problems of previously published clocking schemes
Keywords
combinational circuits; critical path analysis; logic CAD; logic design; timing circuits; combinational circuits; critical path analysis tools; optimal clocking schemes; path analysis approach; path sensitization; sequential systems clocking; Capacitors; Clocks; Combinational circuits; Delay; Digital systems; Feedback; Laboratories; Performance analysis; Sequential circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location
Brighton
Print_ISBN
0-8186-7156-4
Type
conf
DOI
10.1109/EURDAC.1995.528553
Filename
528553
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