CMOS-compatible three dimensional buried channel technology (3DBCT)

This paper reports the development of a single-mask CMOS-compatible process for creating three dimensional buried channels (3DBCT). The structures are formed in silicon using isotropic SF6 plasma etching in a deep reactive ion etcher and are then sealed by depositing a low-stress dielectric material using low-temperature plasma enhance chemical vapor deposition. Utilizing reactive ion etch lag, this bulk micromachining technique creates silicon channels with 3D variability. With a single mask and a single etch step, silicon microchannels are created with control in all three dimensions to form complex muTAS comprising microchannels and cavities with varying depths and width. This technique also allows for creating microfluidic access ports to the microchannels.