An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS

Author

Sonntag, Jeff ; Stonick, John ; Gorecki, James ; Beale, Bill ; Check, Bill ; Gong, Xue-Mei ; Guiliano, Joe ; Lee, Kyong ; Lefferts, Bob ; Martin, David ; Moon, Un-Ku ; Sengir, Amber ; Titus, Stephen ; Wei, Gu-Yeon ; Weinlader, Dan ; Yang, Yaohua

Author_Institution

Accelerant Networks Inc., Beaverton, OR, USA

fYear

2002

fDate

2002

Firstpage

363

Lastpage

366

Abstract

This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The paper focuses on the implementation of the equalizer and the adaptation algorithms, and includes measured results. The 17 mm² device is implemented in a 0.25 μm CMOS process, operates on 2.5 V and 3.3 V supplies and consumes 1.2 W.

Keywords

CMOS integrated circuits; adaptive equalisers; data communication equipment; digital-analogue conversion; error statistics; pulse amplitude modulation; transceivers; 0.25 micron; 1.2 W; 2.5 V; 3.3 V; 5 Gbit/s; 50 in; BER; CMOS process; FR4 backplanes; PAM four level signalling; PAM-4 signalling; adaptation algorithms; adaptive PAM-4 backplane transceiver; backplane connectors; continuously adaptive transmit based equalization; equalizer implementation; pulse amplitude modulation; Backplanes; Convergence; Counting circuits; Delay; Driver circuits; Engines; Equalizers; Intersymbol interference; Round robin; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012844

Filename

1012844