Title :
A 128-phase delay-locked loop with cyclic VCDL
Author :
Chien-Hung Kuo ; Yu-Chieh Ma
Author_Institution :
Dept. of Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taipei, Taiwan
Abstract :
A multiphase delay-locked loop with cyclic voltage controlled delay line is presented in this paper. The 128 output phases can be simultaneously produced by the 16-delay units of VCDL. The presented multi-phase DLL is realized by CMOS 90 nm 1P9M process. The total power consumption is 9.2 mW at the supply voltage of 1.2 V and the operational frequency of 92.16 MHz.
Keywords :
CMOS integrated circuits; delay lock loops; 128-phase delay-locked loop; CMOS; cyclic VCDL; cyclic voltage controlled delay line; multiphase delay-locked loop; Clocks; Delays; Detectors; Generators; Jitter; Phase frequency detector; Voltage control; Clock generator; Cyclic VCDL; Multi-phase DLL;
Conference_Titel :
Quality Electronic Design (ASQED), 2013 5th Asia Symposium on
Conference_Location :
Penang
Print_ISBN :
978-1-4799-1312-1
DOI :
10.1109/ASQED.2013.6643555
