DocumentCode
1855261
Title
Detecting resistive-opens in RRAM using Programmable DfT scheme
Author
Haron, Nor Zaidi ; Arshad, Naveed ; Herman, Sukreen Hana
Author_Institution
Univ. Teknikal Malaysia Melaka, Durian Tunggal, Malaysia
fYear
2013
fDate
26-28 Aug. 2013
Firstpage
22
Lastpage
26
Abstract
Resistive Random Access Memory (RRAM) is one of the emerging memory devices that possesses a combined attribute of SRAM, DRAM and flash. However, as the technology and fabrication process of such a promising memory devices are still immature, RRAM is expected to be impacted by process-variation faults such as resistive-open. This kind of defect is difficult to be detected using existing Design-for-Testability (DfT) scheme, which is developed based on a single critical defect value. This paper presents a new DfT scheme with the capability to identify faulty RRAM cells impacted by resistive-opens due to process variation. The new DfT scheme, referred to as Programmable Low Write Voltage (PLWV), is based on multiple voltage levels that can be programmed to suit the target fault coverage. The concept, design methodology and circuit are described. SPICE simulation results suggest that the proposed PLWV scheme can detect faults with different defect values at minimal circuit modification.
Keywords
DRAM chips; SPICE; SRAM chips; design for testability; flash memories; DRAM; PLWV; RRAM; SPICE simulation; SRAM; circuit modification; design-for-testability; flash; programmable DfT scheme; programmable low write voltage; resistive random access memory; resistive-opens detection; CMOS integrated circuits; Circuit faults; Integrated circuit modeling; Memristors; Random access memory; Simulation; Transistors; Design-for-Testability; Memory defects; RRAM; memory test; memristor;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ASQED), 2013 5th Asia Symposium on
Conference_Location
Penang
Print_ISBN
978-1-4799-1312-1
Type
conf
DOI
10.1109/ASQED.2013.6643558
Filename
6643558
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