Mapping of symmetric and partially-symmetric functions to the CA-type FPGAs

Author

Chrzanowska-Jeske, M. ; Wang, Z.

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

Volume

1

fYear

1995

fDate

13-16 Aug 1995

Firstpage

290

Abstract

This paper presents a new approach to technology mapping of symmetric and partially-symmetric logic functions to Fine-Grain Cellular-Architecture FPGAs. The method is based on Ordered Binary Decision Diagrams (BDDs). Properties of symmetric functions are used to generate Reduced Ordered BDDs for symmetric and partially symmetric functions that can be easily mapped to the rectangular, locally connected arrays of CA-type FPGAs. The mapping method is presented for the existing FPGA architecture, and routing domain modification is suggested for improved mapping. Examples of FPGA layouts are given

Keywords

Boolean functions; cellular arrays; field programmable gate arrays; integrated circuit layout; logic design; network routing; FPGA layouts; binary decision diagrams; cellular architecture FPGAs; fine-grain cellular-architecture; logic functions mapping; partially-symmetric functions; rectangular locally connected arrays; reduced ordered BDD; routing domain modification; symmetric functions; Binary decision diagrams; Binary trees; Boolean functions; Circuit synthesis; Data structures; Field programmable gate arrays; Logic arrays; Logic design; Logic functions; Programmable logic arrays; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-7803-2972-4

Type

conf

DOI

10.1109/MWSCAS.1995.504434

Filename

504434