DocumentCode
1855284
Title
A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS
Author
Clara, Martin ; Wiesbauer, Andreas ; Kuttner, Franz
Author_Institution
Design Centers Austria GmbH, Infineon Technol. AG, Villach, Austria
fYear
2002
fDate
2002
Firstpage
437
Lastpage
440
Abstract
A two-step ADC with interleaved fine conversion achieves 9.1 effective bits with a sampling frequency of 160 MHz. The effective resolution exceeds 8.5 bits for signal frequencies up to 66 MHz. The 10 bit converter with on-chip driver and reference measures only 1 mm2 in a standard 0.18 μm CMOS process and consumes 190 mW from a single 1.8 V supply. The fully embedded design is targeted at SoC-integration.
Keywords
CMOS integrated circuits; analogue-digital conversion; interpolation; system-on-chip; 0.18 micron; 1.8 V; 10 bit; 160 MHz; 190 mW; CMOS process; SoC integration; embedded two-step ADC; interleaved fine conversion; on-chip driver; on-chip reference; parallel-type distributed sample/hold; sampling frequency; subranging architecture; Capacitors; Clocks; Delay; Energy consumption; Interpolation; Preamplifiers; Sampling methods; Signal resolution; Signal sampling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN
0-7803-7250-6
Type
conf
DOI
10.1109/CICC.2002.1012868
Filename
1012868
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