• DocumentCode
    1855383
  • Title

    An improved floor planning algorithm using topological constraint reduction

  • Author

    Asato, Blaine A. ; Ali, Hesham H.

  • Author_Institution
    Dept. of Comput. Sci., Nebraska Univ., Omaha, NE, USA
  • Volume
    1
  • fYear
    1995
  • fDate
    13-16 Aug 1995
  • Firstpage
    310
  • Abstract
    In Vijayan and Tsay (1991) proposed a topological constraint based approach for finding an floor plan with minimal area of a set of blocks from a relative placement. In this paper, we propose a new floor planning algorithm by modifying the constraint based approach. The new algorithm reduces the size of the final layout by removing all redundant edges rather than removing only the edges on the critical path. Our experiments showed that the improved algorithm provides an average of 20 percent better reduction in the total layout area
  • Keywords
    VLSI; circuit layout CAD; integrated circuit layout; network topology; IC design; VLSI layout; floor planning algorithm; minimal area; topological constraint reduction; Computer science; Costs; Law; Legal factors; Routing; Shape; Simulated annealing; Upper bound; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
  • Conference_Location
    Rio de Janeiro
  • Print_ISBN
    0-7803-2972-4
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1995.504439
  • Filename
    504439