• DocumentCode
    1855738
  • Title

    A new TSV set architecture for high reliability

  • Author

    Jaeseok Park ; Sungho Kang

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
  • fYear
    2013
  • fDate
    26-28 Aug. 2013
  • Firstpage
    123
  • Lastpage
    126
  • Abstract
    Recently, 3D IC design is a very attracting issue, and the importance of system reliability increases. This paper proposes a new reliable and repairable TSV set architecture. The proposed architecture supports the previous TSV repair scheme using TSV redundancies and provides a defect/error detection function reutilizing residual TSV redundancies for high reliability of 3D ICs. This can be applied to both online test and soft error detection/analysis. The results show that the proposed TSV set architecture guarantees high TSV redundancy efficiency and reliability. And, the results show that the proposed TSV architecture achieves defect/error coverages which are steady and predictable by a simple formula.
  • Keywords
    integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; radiation hardening (electronics); three-dimensional integrated circuits; 3D IC design; TSV redundancy efficiency; TSV set architecture; integrated circuit; pre-bond post-bond tests; repair ability; repair scheme; signal shifting; soft error detection analysis; system reliability; through silicon via; vertical electrical connection; Circuit faults; Maintenance engineering; Redundancy; Three-dimensional displays; Through-silicon vias; 3D IC; TSV; redundancy; reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ASQED), 2013 5th Asia Symposium on
  • Conference_Location
    Penang
  • Print_ISBN
    978-1-4799-1312-1
  • Type

    conf

  • DOI
    10.1109/ASQED.2013.6643574
  • Filename
    6643574