DocumentCode
1855788
Title
High precision programmable adaptive digital frequency multiplier
Author
Partida, M.A. ; De Luca, A. ; Delgado-Frias, Jose G. ; Goddard, J. ; Parrazales, R.U.
Author_Institution
Dept. of Digital Control, Inst. Politecnico Nacional, Mexico City, Mexico
Volume
1
fYear
1995
fDate
13-16 Aug 1995
Firstpage
385
Abstract
This paper presents and justifies the use of an architecture which increases the precision in the output pulse of an adaptive frequency multiplier. This is done without using a correction circuit, a component which was necessary in previous work in the area
Keywords
adaptive signal processing; digital circuits; frequency multipliers; digital frequency multiplier; high precision type; output pulse; programmable adaptive multiplier; Circuits; Clocks; Counting circuits; Error correction; Feeds; Frequency; Frequency conversion; Neural networks; Proposals; Pulse generation; Signal generators; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
Conference_Location
Rio de Janeiro
Print_ISBN
0-7803-2972-4
Type
conf
DOI
10.1109/MWSCAS.1995.504457
Filename
504457
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